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T1.timing

Click here to read more about T1.timing.

Supported processors, compilers

Each row in the table below represents one set of T1 libraries specific to a certain processor core and a certain compiler.
Silicon/IP
Vendor
Core Compiler Availability
(Variant ID)
ISO26262
Version
Available
Controller Examples
Infineon TC1.6.X Tasking V3.3.x.x (57) V3.4.0.0 TC2xx, TC3xx
Infineon TC1.6.X HighTec GCC V3.3.x.x (15) V3.4.0.0 TC2xx, TC3xx
Infineon TC1.6.X Wind River V3.1.x.x (60)

TC2xx, TC3xx
Infineon TC1.6.X Green Hills V3.1.x.x (73)

TC2xx, TC3xx
NXP/STM e200z0-z4, z6, z7 Green Hills V3.3.x.x (54) / On Request (65/72)

MPC57xx, MPC56xx, MPC55xx, SPC58, SPC57, SPC56, etc.
NXP/STM e200z2, z4, z7 HighTec GCC V3.3.x.x (44) V3.4.0.0 MPC57xx, MPC56xx, MPC55xx, SPC58, SPC57, SPC56, etc.
NXP/STM e200z2, z4, z7 Wind River V3.1.x.x (56) V3.4.0.0 MPC57xx, MPC56xx, MPC55xx, SPC58, SPC57, SPC56, etc.
Arm ARMv7-R: Cortex-R4, Cortex-R4F, Cortex-R5F Texas Instruments V2.5.8.0 (39)

TMS570LS02x/03x/04x/05x/07x, TMS570LS11x/12x/21x/31x, TMS570LC43x, etc.
Arm ARMv7-R: Cortex-R4, Cortex-R4F, Cortex-R5F Green Hills V3.1.x.x (78)

TMS570LS02x/03x/04x/05x/07x, TMS570LS11x/12x/21x/31x, TMS570LC43x, etc.
Arm ARMv7-R: Cortex-R4, Cortex-R4F, Cortex-R5F HighTec GCC V3.3.x.x (77)

TMS570LS02x/03x/04x/05x/07x, TMS570LS11x/12x/21x/31x, TMS570LC43x, etc.
Arm ARMv8-R: Cortex-R52 HighTec CLANG Short Notice (87)

ST Stellar, NXP S32S
Arm ARMv8-R: Cortex-R52 Green Hills V3.3.x.x (85) V3.4.0.0 ST Stellar, NXP S32S
Arm ARMv7-M: Cortex-M3, Cortex-M4 *, Cortex-M7 * GCC V3.3.x.x (82)

Infineon Traveo II, LPC17xx, STM32F4xx, Atmel SAM V71, etc.
Arm ARMv7-M: Cortex-M3, Cortex-M4 *, Cortex-M7 * Green Hills V3.3.x.x (83) V3.4.0.0 Infineon Traveo II, LPC17xx, STM32F4xx, Atmel SAM V71, etc.
Arm ARMv7-M: Cortex-M3, Cortex-M4 *, Cortex-M7 * Keil On Request (84)

Infineon Traveo II, LPC17xx, STM32F4xx, Atmel SAM V71, etc.
Renesas RH850 G3K/G3KH/G3M/G3MH/G4MH Green Hills V3.1.x.x (52) V3.4.0.0 RH850/C1x, RH850/F1x, RH850/P1x, RH850/E2x, etc.
Renesas RH850 G3K/G3KH/G3M/G3MH/G4MH Wind River On Request (53)

RH850/C1x, RH850/F1x, RH850/P1x, RH850/E2x, etc.
(*) Cortex-M4 adds DSP and FPU to Cortex-M3. Cortex-M7 further adds a 64-bit bus and double precision FPU. T1 uses the shared sub-set of the instruction sets.

Supported RTOSs

Vendor Operating System
Customer Any in-house OS**
Customer No OS - scheduling loop plus interrupts**
Elektrobit EB tresos AutoCore OS
Elektrobit EB tresos Safety OS
ETAS RTA-OS
GLIWA gliwOS
HighTec PXROS-HR
Hyundai AutoEver Mobilgene
KPIT Cummins KPIT**
Mentor VSTAR OS
Micriμm μC/OS-II**
Vector MICROSAR-OS***
FreeRTOS**
(**) T1 OS adaptation package T1-ADAPT-OS required.
(***) T1 OS adaptation package T1-ADAPT-OS required if 'OS Timing Hooks' are not supported.

Supported target interfaces

Target Interface Comment
CAN Low bandwidth requirement: typically one CAN message every 1 to 10ms. The bandwidth consumed by T1 is scalable and strictly deterministic.
CAN FD Low bandwidth requirement: typically one CAN message every 1 to 10ms. The bandwidth consumed by T1 is scalable and strictly deterministic.
Diagnostic Interface The diagnostic interface supports ISO14229 (UDS) as well as ISO14230, both via CAN with transportation protocol ISO15765-2 (addressing modes 'normal' and 'extended'). The T1-HOST-SW connects to the Diagnostic Interface using CAN.
Ethernet (IP/UDP) UDP is used, IP-address and port can be configured.
FlexRay FlexRay is supported via the diagnostic interface and a CAN bridge.
JTAG/DAP Interfaces exist to well-known debug environments such as Lauterbach TRACE32 and iSYSTEM winIDEA. The T1 JTAG interface requires an external debugger to be connected and, for data transfer, the target is halted. TriCore processors use DAP instead of JTAG.

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T1.posix

Click here to read more about T1.posix.

Supported processors, compilers

Each row in the table below represents one set of T1 libraries specific to a certain processor core and a certain compiler.
Silicon/IP
Vendor
Core Compiler Availability
(Variant ID)
ISO26262
Version
Available
Controller Examples
Arm ARMv8-A: Cortex-A5x, Cortex-A7x GCC V3.1.3.1 (252/253)

NVIDIA Tegra, NXP S32G, TI TDAx, etc.
Intel x86 64-bit GCC V3.1.3.1 (254/255)

Intel Atom Denverton, etc.

Supported RTOSs

Vendor Operating System
Elektrobit EB corbos Linux
BlackBerry QNX7
Various Vendors Embedded Linux (e.g. Yocto), Kernel >= 4.14

Supported target interfaces

Target Interface Comment
Ethernet (IP/UDP) UDP is used, IP-address and port can be configured.

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T1.accessPredictor

Click here to read more about T1.accessPredictor.

Supported processors

Silicon/IP
Vendor
Core Controller Examples
Infineon TC1.6.X TC2xx, TC3xx
NXP/STM e200z0-z4, z6, z7 MPC57xx, MPC56xx, MPC55xx, SPC58, SPC57, SPC56, etc.

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T1.stack

Click here to read more about T1.stack.

Supported processors

Silicon/IP
Vendor
Core Controller Examples
Infineon TC1.6.X TC2xx, TC3xx
NXP/STM e200z0-z4, z6, z7 MPC57xx, MPC56xx, MPC55xx, SPC58, SPC57, SPC56, etc.
Arm ARMv7-R: Cortex-R4, Cortex-R4F, Cortex-R5F TMS570LS02x/03x/04x/05x/07x, TMS570LS11x/12x/21x/31x, TMS570LC43x, etc.
Arm ARMv8-R: Cortex-R52 ST Stellar, NXP S32S
Arm ARMv7-M: Cortex-M3, Cortex-M4 *, Cortex-M7 * Infineon Traveo II, LPC17xx, STM32F4xx, Atmel SAM V71, etc.
Renesas RH850 G3K/G3KH/G3M/G3MH/G4MH RH850/C1x, RH850/F1x, RH850/P1x, RH850/E2x, etc.
Intel x86 64-bit Intel Atom Denverton, etc.
(*) Cortex-M4 adds DSP and FPU to Cortex-M3. Cortex-M7 further adds a 64-bit bus and double precision FPU. T1 uses the shared sub-set of the instruction sets.
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The practice-oriented, book on methodology and analysis of embedded software timing. Numerous case studies help to avoid tricky problems, facilitate optimal use of processor resources and give many hints to secure correct runtime behavior.

Edited by Springer. Available as printed edition and eBook. Take a closer look here.
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T1 supports TC39x
Synchronized traces from 6 cores!
T1 makes it happen. Click here, to view a screenshot of T1 with 6 synchronized traces and some cross-core communications.

AURIX TC399

More details on the AURIX 2G can be found in Infineon's official press-release.
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