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Publications and more

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PDF EN          A systematic approach for timing requirements
Manuscript of a presentation at the EMCC (Embedded Multi-Core Conference) 2018 in Munich
Author: Dipl.-Ing. (BA) Peter Gliwa, GLIWA
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         Multi-core poster
Multi-core processors have conquered the automotive industry faster than expected a few years ago. As practice shows, one has to count the cost if one lacks of multi-core knowledge base. Our multi-core poster summarizes the contents of our Multi-core training in one DIN-A1 sized paper. Besides theoretical basics there are examples of current architectures as well as explanations of different kinds of parallelism, cloning, spinlocks, AUTOSAR aspects and not least a glossary. We would be pleased to send you the poster as a hardcopy. Just contact us.

         Timing Poster
What is embedded timing and how can correct timing be secured? Our DIN-A1-sized timing poster sheds light on this complex topic. Various aspects of the development process are illuminated such as diverse analysis techniques, standard, AUTOSAR mechanisms and much more.
We would be delighted to send you a hard-copy of the poster. Just get in touch with us.
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PDF EN          Timing Analysis and Timing Verification today and in the future
Subtitle: "Does reality matter?"
Manuscript of a presentation at the 18th EUROFORUM 2014 in Munich
Author: Dipl.-Ing. (BA) Peter Gliwa, GLIWA
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PDF DE          Measurement of application performance on automotive microprocessors
Manuscript (German only) of a presentation at VDI Wissensforum "Elektronik im Kraftfahrzeug" 2011 in Baden-Baden
Authors: Dipl.-Ing. (BA) Peter Gliwa, GLIWA and
Dr.-Ing. Albrecht Mayer, Infineon Technologies AG
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PDF EN          Tool Support for Seamless System Development based on AUTOSAR Timing Extensions
Manuscript of a presentation at ERTS 2012 in Toulouse (ERTS = Embedded Real Time Software Exhibition and Congress)
Authors: Dr. Oliver Scheickl, BMW Car IT GmbH,
M.Sc. Christoph Ainhauser, BMW Car IT GmbH and
Dipl.-Ing. (BA) Peter Gliwa, GLIWA
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PDF DE          Future verification of timing requirements in complex E/E-systems
Manuscript (German only) of a presentation at AutoTest 2012 in Stuttgart
Authors: Dipl.-Ing. (BA) Peter Gliwa, GLIWA and
Dipl.-Ing. Ralf Klein, Symtavision GmbH
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PDF EN          Virtualisation in Use – An AURIX / T1 demo
Slides of a presentation at ESE Kongress 2012 in Sindelfingen (ESE = Embedded Software Engineering)
Authors: Dr. Nicholas Merriam, GLIWA,
Dipl.-Ing. (BA) Peter Gliwa, GLIWA and
Dipl.-Ing. Jens Harnisch, Infineon Technologies AG
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         Timing analysis for the early verification of software
Article in ATZelektronik 01/2009
Authors: Dipl.-Ing. (BA) Peter Gliwa, GLIWA,
Dipl.-Ing. Hans Sarnowski, BMW AG,
Dr. Marek Jersak, Symtavision and
Dr. Kai Richter, Symtavision
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         The challenges for software developers
Article (German only) on multi-core in 07/2013.
We at GLIWA would like to change the "[not sufficiently available]" in the article's first sentence to "[not sufficiently wide-spread]". Our timing suite T1 fits exactly the gap in the tools sketched out by the article.
Author: Corinne Schindlbeck,
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         Bibliography for cross-references
If you need to cite a document on this page, you can download the bibliography here.

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Embedded World 2019

Visit us at the Embedded World from February, 26th - 28th, 2019, hall 4, stand 4-570

NEW product T1.accessPredictor
Upset by MPU exceptions in the field? T1.accessPredictor allows you to check for any memory access violations before even flashing the software. It will perform a static analysis by disassembling the binary, building up the call-tree and identifying r/w memory accesses for each function. No source code required!

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T1 supports TC39x
Synchronized traces from 6 cores!
T1 makes it happen. Click here, to view a screenshot of T1 with 6 synchronized traces and some cross-core communications.


More details on the AURIX 2G can be found in Infineon's official press-release.

Multi-core in minutes
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The AURIX based ATdemo comes with a multi-core OS, a demo application and built-in T1 timing analysis. It was never easier to get started with multi-core.
Click here for details.
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